As advanced technologies evolve, controlling leakage current becomes more and more important. Currently, in various applications, the bulks of MOS transistors are connected directly to a regular voltage source. For example, the bulks of NMOS transistors are coupled to a first voltage source providing a reference voltage VSS while the bulks of PMOS transistors are coupled to a second voltage source providing an operational voltage VDD. Such configurations, though, result in some leakage current, but the leakage current is acceptable for existing applications in slower semiconductor technology nodes such as 130 nm. For faster applications in advanced semiconductor nodes such as 40 nm, the once-acceptable leakage current is no longer acceptable. New mechanisms are needed to better control the leakage current.
Like reference symbols in the various drawings indicate like elements.